AN-600 Understanding Latch-Up in Advanced CMOS Logic

Application Note 339 Fairchild's Process Enhancements Eliminate the CMOS SCR Latch-Up Problem In 74HC Logic

INTRODUCTION SCR latch-up is a parasitic phenomena that has existed in circuits fabricated using bulk silicon CMOS technologies. The latch-up mechanism, once triggered, turns on a parasitic SCR internal to CMOS circuits which essentially shorts VCC to ground. This generally destroys the CMOS IC or at the very least causes the system to malfunction. In order to make MM54HC/MM74HC high speed CMOS...

Experimental Study and Spice Simulation of Cmos Inverters Latch-up Effects Due to High Power Microwave Interference

Experimental study and SPICE simulation of CMOS digital circuits latch-up effects due to high power microwave interference are reported in this paper. As a traditional inherent destruction phenomenon, latch-up effect may jeopardize the correct function of the circuits, and could be triggered in various ways such as ESD pulse, cosmic ray, heavy ion particles etc. Through the directly injected ex...

Fairchild’s Process Enhancements Eliminate the CMOS SCR Latch-Up Problem In 74HC Logic

Fairchild’s Process Enhancements Eliminate the CMOS SCR Latch-Up Problem In 74HC Logic

A Novel Low Power Pulsed Latch with Increased Reliability

The maturation in fabrication technologies of semiconductor integrated circuits results in rapidly shrinking technology node and aggressive scaling of voltage causes an increase in the probability of soft errors in advanced CMOS digital logic circuits. Many attempts to mitigate the soft errors ensue in significant cost penalties in terms of area, power and performance. The proposed method inten...